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mosel vitelic 1 v61c518256 32k x 8 high speed static ram preliminary v61c518256 rev. 0.3 july 1998 features n high-speed: 10, 12, 15 ns n low power dissipation: cmos standby: 0.5 ma (max.) n fully static operation n all inputs and outputs directly compatible n three state outputs n ultra low data retention current (v cc = 2v) n single 5v 10% power supply n packages 28-pin tsop (standard) 28-pin 300 mil soj description the v61c518256 is a 262,144-bit static random access memory organized as 32,768 words by 8 bits. it is built with mosel vitelic? high performance cmos process. inputs and three- state outputs are ttl compatible and allow for direct interfacing with common system bus structures. device usage chart operating temperature range package outline access time (ns) temperature mark t n r 101215 0 c to 70 c blank functional block diagram row decoder 512 x 512 memory array input data circuit column i/o column decoder control circuit v cc gnd a 0 a 1 a 6 a 10 518256-01 a 13 a 14 i/o 0 i/o 7 ce oe we a 2 a 12 a 11 a 5
2 v61c518256 rev. 0.3 july 1998 mosel vitelic v61c518256 pin descriptions a 0 ? 14 address inputs these 15 address inputs select one of the 32,768 x 8 bit segments in the ram. ce chip enable inputs ce is an active low input. chip enable must be low when reading from or writing to the device. when high, the device is in standby mode with i/o pins in the high impedance state. oe output enable input the output enable input is active low. when oe is low with ce low and we high, data of the selected memory location will be available on the i/o pins. when oe is high, the i/o pins will be in the high impedance state. we write enable input an active low input, we input controls read and write operations. when ce and we inputs are both low, the data present on the i/o pins will be written into the selected memory location. i/o 0 ?/o 7 data input and data output ports these 8 bidirectional ports are used to read data from and write data into the ram. v cc power supply gnd ground pin configurations (top view) 28-pin soj 28-pin tsop (standard) v cc a 8 a 9 a 11 a 10 oe i/o 0 i/o 1 i/o 2 gnd a 0 a 1 a 2 a 3 a 4 a 5 i/o 7 i/o 6 i/o 5 i/o 4 518256-01 a 13 we 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a 14 a 12 a 6 a 7 i/o 3 ce oe a11 a9 a8 a13 we vcc a14 a12 a7 a6 a5 a4 a3 a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 22 23 24 25 26 27 28 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 518256-03
mosel vitelic v61c518256 3 v61c518256 rev. 0.3 july 1998 part number information absolute maximum ratings (1) note: 1. stresses greater than those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliabili ty. symbol parameter commercial units v cc supply voltage -0.5 to +7 v v n input voltage -0.5 to +7 v v dq input/output voltage applied v cc + 0.5 v t bias temperature under bias -55 to +85 c t stg storage temperature -55 to +125 c sram family c = cmos process 61 = standard 51 = 5v operating voltage 256k organization pkg speed 518256-05 pwr. 61 c 8 51 256 mosel-vitelic manufactured v 8 = 8-bit 10 ns 12 ns 15 ns temp. blank = 0 ? c to 70 ? c blank = standard t = tsop standard r = 300-mil soj density capacitance* t a = 25 c, f = 1.0mhz note: * this parameter is guaranteed by design and not tested. truth table note: x = don? care, l = low, h = high symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out output capacitance v i/o = 0v 8 pf mode ce oe we i/o operation standby h x x high z read l l h d out read l h h high z write l x l d in
4 v61c518256 rev. 0.3 july 1998 mosel vitelic v61c518256 dc electrical characteristics (over all temperature ranges, v cc = 5v 10%) notes: 1. these are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. v il (min.) = -3.0v for pulse width < 20ns. 3. f max = 1/t rc . 4. maximum values. symbol parameter test conditions min. typ. max. units v il input low voltage (1,2) -0.5 0.8 v v ih input high voltage (1) 2.2 6 v i il input leakage current v cc = max, v in = 0v to v cc -5 5 m a i ol output leakage current v cc = max, ce = v ih , v out = 0v to v cc -5 5 m a v ol output low voltage v cc = min, i ol = 8ma 0.4 v v oh output high voltage v cc = min, i oh = -4ma 2.4 v symbol parameter com. (4) ind. units i cc1 average operating current, ce v il output open, v cc = max., f = f max (3) 110 130 ma i sb ttl standby current ce 3 v ih , v cc = max. 25 40 ma i sb1 cmos standby current, ce 3 v cc ?0.2v, v in 3 v cc ?0.2v or v in 0.2v, v cc = max. 12ma
mosel vitelic v61c518256 5 v61c518256 rev. 0.3 july 1998 data retention characteristics notes: 1. t rc = read cycle time 2. t a = +25 c. low v cc data retention waveform symbol parameter min. typ. (2) max. units v dr v cc for data retention ce 3 v cc ?0.2v 2.0 5.5 v i ccdr data retention current v dr = 3.0v, ce 3 v dr ?0.2v com? 150 m a ind. 200 t cdr chip deselect to data retention time 0 ns t r operation recovery time (see retention waveform) t rc (1) ns v cc 518256-07 data retention mode v dr ce 2.2v 2.2v 4.5v t cdr t r v dr 3 2v 4.5v ac test conditions ac test loads and waveforms key to switching waveforms input pulse levels 0 to 3v input rise and fall times 3 ns timing reference levels 1.5v output load see below +5v 480 ? 480 ? 255 ? * includes scope and jig capacitance i/o pin c l = 30 pf* +5v 255 ? output load for t clz , t chz , t ohz , t olz , t wz , t ow i/o pin 5 pf* 518256-06 waveform inputs outputs must be steady will be steady may change from h to l will be changing from h to l may change from l to h will be changing from l to h don't care: any change permitted changing: s tat e unknown does not apply center line is high impedance ?ff state
6 v61c518256 rev. 0.3 july 1998 mosel vitelic v61c518256 ac electrical characteristics (over all temperature ranges) read cycle write cycle parameter name parameter -10 -12 -15 unit min. max. min. max. min. max. t rc read cycle time 10 12 15 ns t aa address access time 10 12 15 ns t acs chip enable access time 10 12 15 ns t oe output enable to output valid ???ns t clz chip enable to output in low z 2??ns t olz output enable to output in low z 0??ns t chz chip disable to output in high z 020304ns t ohz output disable to output in high z 020304ns t oh output hold from address change 2??ns parameter name parameter -10 -12 -15 unit min. max. min. max. min. max. t wc write cycle time 10 12 15 ns t cw chip enable to end of write 9 10 12 ns t as address setup time 0??ns t aw address valid to end of write 9 10 12 ns t wp write pulse width 8?11ns t ah address hold from end of write 0.5 0.5 0.5 ns t whz write to output high-z 050505ns t dw data setup to end of write 6??ns t dh data hold from end of write 0??ns t ow output active from end of write 3??ns
mosel vitelic v61c518256 7 v61c518256 rev. 0.3 july 1998 switching waveforms (read cycle) read cycle 1 (1, 2) read cycle 2 (1, 2, 4) read cycle 3 (1, 3, 4) notes: 1. we = v ih . 2. ce = v il . 3. address valid prior to or coincident with ce transition low. 4. oe = v il . 5. transition is measured 500mv from steady state with c l = 5pf. this parameter is guaranteed and not 100% tested. address 518256-08 oe i/o t rc t aa t oe t olz t ohz (5) address i/o 518256-09 t rc t aa t oh t oh address 518256-10 i/o ce t acs t clz (5) t chz (5)
8 v61c518256 rev. 0.3 july 1998 mosel vitelic v61c518256 switching waveforms (write cycle) write cycle 1 (we controlled) (4) write cycle 2 (ce controlled) (4) notes: 1. the internal write time of the memory is defined by the overlap of ce active and we low. both signals must be active to initiate and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. t ah is measured from the earlier of ce or we going high. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the outputs must not be a pplied. 4. oe = v il or v ih . however it is recommended to keep oe at v ih during write cycle to avoid bus contention. 5. if ce is low during this period, i/o pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 6. t cw is measured from ce going low to the end of write. address output input ce we 518256-11 t wc t cw (6) t dw t dh t aw t ah (2) t whz (3) t wp (1) t as address output input ce we 518256-12 t wc t dw t dh t aw t ah (2) hi-z t as (5) t cw (6)
mosel vitelic v61c518256 9 v61c518256 rev. 0.3 july 1998 package diagrams 28-pin 300 mil soj 28-pin tsop 0.715 0.015 (1) [18.161 0.381] 0.020 min [0.508 min] 0.134 0.006 [3.404 0.152] 0.100 0.005 [2.540 0.127] 0.300 (1) 0.334 0.013 [8.484 0.330] 28 1 15 14 0.265 0.020 [6.731 0.508] 0.011 0.003 [0.279 0.076] unit in inches [mm] 0.029 0.003 [0.737 0.076] 0.034 0.011 [0.836 0.279] 0.019 0.003 [0.483 0.076] 0.050 typ [1.270 typ] +0.005 ?.008 7.620 +0.127 ?.203 (1) does not include mold flash protrusion and should be measured from the bottom of the package. 0.004 [0.102] 0.528 0.008 [13.41 0.203] 0.020 +0.007 ?.008 0.508 +0.178 ?.305 0.006 0.002 [0.152 0.051] 0.315 0.004 [8.00 0.102] 0.046 0.004 [1.17 0.102] 0.006 0.004 [0.152 0.102] unit in inches [mm] 0.022 [0.559] bsc 0.463 0.003 [11.76 0.076]
10 v61c518256 rev. 0.3 july 1998 mosel vitelic v61c518256 notes
mosel vitelic v61c518256 11 v61c518256 rev. 0.3 july 1998 notes
mosel vitelic worldwide offices v61c518256 u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 011-852-665-4883 fax: 011-852-664-7535 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 011-886-2-545-1213 fax: 011-886-2-545-1209 1 creation road i science based ind. park hsin chu, taiwan, r.o.c. phone: 011-886-35-783344 fax: 011-886-35-792838 japan wbg marine west 25f 6, nakase 2-chome mihama-ku, chiba-shi chiba 261-71 phone: 011-81-43-299-6000 fax: 011-81-43-299-6555 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 southwestern suite 200 5150 e. pacific coast hwy. long beach, ca 90804 phone: 562-498-3314 fax: 562-597-2174 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. ?copyright 1997, mosel vitelic inc. 7/98 printed in u.s.a. mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 u.s. sales offices

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